Exemplary embodiments relate generally to a semiconductor memory apparatus and a method of operating the same and, more particularly, to a semiconductor memory apparatus including a plurality of memory blocks and a method of operating the same.
A semiconductor memory apparatus performs one of program, read, and erase operations of selected memory cells in response to a row address and a column address.
More particularly, the semiconductor memory apparatus generally includes a plurality of memory blocks, and one of the plurality of memory blocks is selected in response to a block address included in the row address. Each of the memory blocks generally includes a plurality of word lines, and one of the plurality of word lines is selected in response to a word line address included in the row address. Furthermore, one or more of cells coupled to the selected word line are selected in response to the column address. The selected cells can include a memory cell, a redundancy cell, a repair cell, and a flag cell.
In cases where the semiconductor memory apparatus inputs and outputs data of 8 bytes, one memory block includes at least first to eighth I/O blocks. Furthermore, each of the I/O blocks includes 1024 bit lines (that is, 1024 columns). Accordingly, 8192 (1024×8) memory cells are coupled to one word line. If a large number of the memory cells are coupled to one word line as described above, the length of the word line can become long. Wirings to which voltages for the operations of memory cells are supplied are coupled to the word line. An operating voltage of a low level is supplied to a memory cell which is far from a portion where the word line and the wirings are coupled together because of the resistance component of the word line.
Furthermore, interference can be generated between the word line and the wirings according to the arrangement of the memory blocks and a row decoder for selecting one of the memory blocks. Consequently, the operating voltage supplied to the word line can be changed.
Meanwhile, with an increase of the number of memory blocks included in a semiconductor memory apparatus, the size of a row decoder for selecting one or the memory blocks is typically increased. If the area occupied by the row decoder is increased within a limited memory chip, the area where the memory blocks are formed is reduced, affecting the degree of integration.